AI runs short of memory and storage
AI training and inference are consuming memory and storage faster than manufacturers can add capacity. High-bandwidth memory for accelerators takes far more wafer area per bit than standard DRAM, so every HBM line that comes online crowds out server and PC DRAM supply. At the same time, inference caches and AI data lakes are pulling enterprise SSDs and nearline hard drives out of a market that was not built for this volume. The result is tightening supply, with prices and margins rising across DRAM, NAND and HDD at once. A portfolio under this thesis selects the companies that make memory and storage: DRAM and NAND producers, hard-drive manufacturers, and the suppliers they depend on to ship volume, including memory interface chip designers and memory test equipment makers. AI accelerator makers are buyers of this memory, not beneficiaries of its scarcity, and are left out.
Seagate is one half of the hard-drive duopoly with Western Digital, vertically integrated from heads and media to finished drives. its fy2026 10-K reports 789 exabytes of HDD capacity shipped on $12.2bn revenue at 46% gross margin, and states the vast majority of the business comes from data center markets — nearline drives sold to hyperscalers and large enterprises. third-party coverage of the september 2026 quarter puts data center at roughly 81% of sales and datacenter customers at about 90% of shipped capacity, with 198 of 220 exabytes nearline. non-HDD lines (systems, a small SSD business) are immaterial. this is exactly leg 2 of the thesis: nearline exabyte demand filling capacity on a fixed cost base, with HAMR raising revenue per unit. gross margin moved from 35% to 46% year on year as pricing and utilisation improved. pure play HDD producer → 1.0.
Western Digital is a pure hard-disk-drive maker since the February 2025 spin-off of its NAND business as Sandisk; its homepage now carries the HDD business unit only. in fiscal Q1 2027 (quarter ended 2 October 2026) revenue was $4.38 billion, cloud was about $3.9 billion or 88% of total, and 223 of 248 exabytes shipped were nearline — the exact product the hard-drive leg of the thesis names. the thesis channel is visible in the numbers: ASP per terabyte up 28% year on year, gross margin 58%, with capacity-point transitions (ePMR, 40TB platform) lifting revenue per unit without proportional capex. essentially all revenue and the whole profit swing come from HDDs, and roughly nine-tenths of bits go to data-center nearline, so against the hard-drive-manufacturers angle this is a pure play → 1.0.
Micron is a vertically integrated memory producer: essentially all revenue is DRAM and NAND sold into data center, mobile, pc, auto and industrial markets, with a small NOR line. fiscal q4 2026 (ended september 2026) revenue was $54.2b, of which DRAM was $39.8b (73%) and NAND $14.1b (26%); fiscal 2026 revenue was $133.2b against $37.4b the prior year, gross margin near 87%, diluted eps $32.93 for the quarter. the swing is pricing on a largely fixed cost base plus mix shift to HBM and data center SSD (SSD nearly $10b, over two-thirds of NAND), which is exactly leg 1 of the thesis. against the DRAM and NAND producers angle there is no non-memory segment to dilute the exposure, so pure play at 1.0. earnings power moves directly with contract prices for DRAM and NAND; sign positive.
Silicon Motion is a fabless designer of NAND flash controllers and NAND-based storage solutions — its single operating segment. q3 2026 revenue was $560.2m at a 53.7% gross margin; management put the mix at roughly 60% controllers (client SSD, eMMC/UFS, MonTitan enterprise SSD) and 40% solutions (Ferri automotive/edge SSDs and enterprise boot drives built on its own controllers). every dollar is NAND-attached, which is exactly this portfolio's angle of NAND and SSD controller designers. the discount from 1.0 reflects the solutions business, where the company buys NAND and passes cost through on six-month contracts, and the consumer controller lines (eMMC/UFS, PC SSD) whose unit volume is currently being squeezed by high memory prices rather than lifted by them. near-pure play for leg 3 → 0.9.
Rambus designs memory interface chips (DDR5 RCD, PMIC, SPD hub, client and SOCAMM2 chipsets) sold to Micron, Samsung and SK hynix for server and client DRAM modules, plus silicon IP (HBM, GDDR, DDR, PCIe, CXL PHYs and controllers, security IP) and patent royalties. in Q3 2026 product revenue, which is almost entirely memory interface chips, was 52% of $218.3m revenue and is the growth engine (up 22% y/y); royalties were about 35%, largely fixed-structure patent and IP licences to memory and SoC makers; contract and other (IP cores, incl. security) was 13%. about half the business is directly memory-attached volume product and a further slice is memory-related IP, which fits the leg-3 interface-designer angle squarely, but the fixed royalty stream and non-memory IP keep it short of pure play → 0.7.