Big Tech designs its own chips
The largest cloud providers are designing their own AI accelerators rather than buying only general-purpose graphics processors. The motive is cost: a chip tuned to one company's workloads can run training and inference more cheaply per unit of compute than a merchant part bought at market prices. Each new generation of these in-house chips is paid for in advance, because the cloud companies do not build them alone. They hire custom-silicon design partners, license interface and processor IP, and book foundry and advanced-packaging capacity, and that spending now recurs with every annual refresh. A portfolio under this thesis selects the companies on the receiving end of those payments: application-specific chip designers that take a hyperscaler's architecture to production, licensors of memory, interconnect and core IP, and the foundries and packaging houses that manufacture the parts. Companies whose earnings depend materially on these programs qualify; makers of general-purpose AI graphics processors are excluded.
Broadcom is the flagship custom-silicon design partner for leg 1: it designs and supplies custom accelerators (XPUs) for Google (TPU), Meta (MTIA), OpenAI (Jalapeño) and Anthropic, six disclosed XPU customers in total, with annual generations (Ironwood TPU v7 → v8i, next-gen OpenAI part approaching tape-out). Q3 FY26 AI semiconductor revenue was $16.7bn of $29.6bn total (56%), guided to $21.7bn of $34.8bn in Q4 (62%); independent reporting puts XPU shipments at 73% of that AI line, so custom accelerators are roughly 41% of company revenue and the largest and fastest-growing line. the rest is AI networking (~15%, adjacent theme), non-AI semis (~14%) and infrastructure software (30%, VMware/CA/Symantec), none of which express the thesis. largest revenue line and the dominant growth driver, but well under the whole business → 0.75, between material and pure play.
TSMC is the world's largest dedicated foundry (about 70% share) and the sole fab and CoWoS packaging venue for essentially every disclosed hyperscaler custom accelerator (Google TPU, AWS Trainium, Meta MTIA, Microsoft Maia) as well as for the merchant GPUs they displace. HPC platform revenue reached 68% of total in Q3 2026 on AI accelerator demand, and advanced nodes (7nm and below) are 77 to 79% of wafer revenue, so the AI accelerator value chain is now the majority of the business. against the foundry and advanced-packaging angle TSMC is the clearest expression, but its exposure to the custom-versus-merchant shift itself is mix-agnostic — it is paid per wafer and per CoWoS slot whether the die is a Broadcom-designed TPU or an Nvidia GPU — and roughly a third of revenue is smartphone, automotive, IoT and consumer. that puts it between material and peripheral: 0.5.
Marvell is a diversified fabless data-infrastructure chip vendor: data center was 79% of q2 fy27 revenue ($2.17bn of $2.74bn), with communications and other the remaining 21%. the thesis leg is its custom silicon unit, which designs and supplies hyperscaler XPUs and XPU-attach parts (disclosed programs with Amazon, Microsoft and an expanded Google agreement carrying a warrant vesting toward $120bn cumulative revenue). custom was about $1.5bn in fy26 — roughly 25% of data center and 18% of group revenue — and management guides a sharp ramp (more than $12bn by fy29, about $30bn by fy31, out of a $70–90bn group target). the larger half of data center today is connectivity (optical DSPs, switching, retimers) that sells into accelerator clusters regardless of merchant-versus-custom mix, so it is adjacent rather than thesis-expressing. custom share is near a fifth and growing fast → material exposure, 0.6, not a pure play.
ASE Technology is the largest outsourced assembly and test (OSAT) house. consolidated revenue splits roughly 62% ATM (packaging and testing) and 38% EMS (contract electronics manufacturing) in Q3 2026. the piece that touches this thesis is LEAP — leading-edge advanced packaging and test for AI and HPC parts, including CoWoS-type 2.5D work licensed from TSMC — which was US$1.6bn in 2025, 13% of ATM and under a tenth of group revenue, guided to double in 2026 and again in 2027. computing was 34% of ATM in Q3 2026. the rest is wirebond and general packaging, mainstream test and EMS, none of which expresses custom silicon. LEAP slots serve merchant GPUs and custom accelerators alike, so exposure is to total accelerator volume, not the custom-versus-merchant mix; the incremental link is overflow packaging demand from parallel hyperscaler ASIC programs. fast-growing but still minority exposure in a diversified OSAT → peripheral, 0.35.